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A 2-trillion-parameter run on Huawei silicon would change the hardware story
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A rumour circulating this morning says DeepSeek is already pretraining V5: roughly two trillion parameters, an ultra-sparse mixture-of-experts model, and — the part that matters — running that pretraining on Huawei's Ascend 950 / 950DT rather than NVIDIA hardware. The same account claims Huawei kernel engineers are physically working inside DeepSeek's offices to keep the cluster running.
Nothing here is confirmed. No paper, no benchmark, no hardware disclosure. Treat every number below as a claim being repeated, not a fact being reported.
Why "ultra-sparse" is the interesting word
A mixture-of-experts model stores many specialist sub-networks and routes each token to only a few of them. Total parameters can be enormous while the compute per token stays modest — you pay for memory and routing, not for multiplying everything by everything.
At two trillion parameters, "ultra-sparse" stops being a detail and becomes the entire engineering problem. The model no longer fits the usual assumptions: experts must be sharded across many devices, tokens must be routed across those devices cheaply, and the interconnect becomes the ceiling rather than the arithmetic units. That is precisely the layer where a non-NVIDIA stack has historically failed.
The model defines the traffic
Ultra-sparse routing sends every token to a handful of experts spread across the cluster — all-to-all communication, not dense matmuls.
The kernels decide the throughput
Attention, routing, collectives and memory movement each need hand-tuned kernels for the specific chip. This is where porting usually dies.
Engineers sit with the model team
The rumour’s kernel engineers on-site is the tell: it implies the software stack was not turnkey and needed co-development.
The run either completes or it does not
A frontier pretraining run is a single, unforgiving test. Partial success is failure, which is why nobody claims it casually.
The hardware claim is the real story
Everyone has watched Chinese labs train on constrained hardware and get surprisingly far. What would be new here is scale: not a fine-tune, not inference, but a frontier pretraining run on domestic silicon.
If that is true, three things follow, none of which require the model to beat anything:
- The CUDA moat erodes at the software layer, not the silicon layer. Porting a large training run is a compiler and kernel project measured in engineer-years. Doing it once proves it can be done again.
- Talent co-location becomes the product. Chip vendors who ship engineers into the customer's office are selling integration, not hardware. That model is closer to how enterprise software gets deployed than how chips usually get sold.
- Export controls get a new counterfactual. Restrictions have been justified partly on the assumption that the leading edge of training requires a specific supply chain. A completed frontier run on Ascend would weaken that assumption — and strengthen the case for controls on tooling and memory instead.
What we would actually watch for
Rumours like this are cheap; the artefacts are not. Watch for a technical report naming the cluster, a throughput figure per chip, or an inference release that only runs well on Ascend. Any one of those would move this from a claim to a datapoint.
We build data and inference systems, and the practical lesson is already clear regardless of whether this particular rumour holds: the portability of a model is a software property, not a hardware one. Teams that treat kernels, routing and memory layout as first-class engineering can move across substrates. Teams that treat them as a vendor's problem cannot move at all.
Source: an unverified rumour circulating on 12 November 2026 about DeepSeek V5 and Huawei Ascend 950/950DT. No primary documentation was available at the time of writing; all figures are as claimed by that account and are not independently confirmed.
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